000 01499cam a22004091i 4500
999 _c79736
_d79736
001 20616547
005 20211106155037.0
006 m |o d |
007 cr_|||||||||||
008 180804s2018 nju ob 001 0 eng
010 _a 2018037473
020 _a9781119313984 (ePub)
020 _a9781119313977 (Adobe PDF)
020 _z9781119314134 (hardcover)
020 _a9781119313991
040 _aDLC
_beng
_erda
_cDLC
_dDLC
042 _apcc
050 1 0 _aTK7870.17
082 0 0 _a621.39/5
_223
245 0 0 _aAdvances in embedded and fan-out wafer level packaging technologies /
_c[edited by] Beth Keser, Ph.D., Steffen Kroehnert.
250 _a1st edition.
264 1 _aHoboken, NJ :
_bWiley,
_c[2018]
300 _a1 online resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bn
_2rdamedia
338 _aonline resource
_bnc
_2rdacarrier
504 _aIncludes bibliographical references and index.
588 _aDescription based on print version record and CIP data provided by publisher.
650 0 _aChip scale packaging.
650 0 _aIntegrated circuits
_xWafer scale integration.
700 1 _aKeser, Beth,
_d1971-
_eeditor.
700 1 _aKroehnert, Steffen,
_d1970-
_eeditor.
856 _yFull text available at Wiley Online Library Click here to view
_uhttps://onlinelibrary.wiley.com/doi/book/10.1002/9781119313991
906 _a7
_bcbc
_corigcop
_d1
_eecip
_f20
_gy-gencatlg
942 _2ddc
_cER