| 000 -LEADER |
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| fixed length control field |
06955cam a22004098i 4500 |
| 001 - CONTROL NUMBER |
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in00024329535 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DLC |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20260601092527.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
t| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
260601s2025 nyu b 001 0 eng |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781394343096 |
| Qualifying information |
hardback |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| Cancelled/invalid ISBN |
9781394343119 |
| Qualifying information |
pdf |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| Cancelled/invalid ISBN |
9781394343102 |
| Qualifying information |
epub |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Cancelled/invalid ISBN |
9781394343126 |
| 041 ## - LANGUAGE CODE |
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| Language code of text/sound track or separate title |
eng |
| 042 ## - AUTHENTICATION CODE |
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| Authentication code |
pcc |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7885.7 |
| Item number |
.P328 2025 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.39/2 |
| Edition number |
23/eng/20250923 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Preferred name for the person |
Pakdel, Majid |
| Relator term |
author |
| Relator code |
aut |
| -- |
http://id.loc.gov/vocabulary/relators/aut |
| Authority record control number |
http://id.loc.gov/authorities/names/n2024055895 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Fundamentals of VHDL for FPGA programming using Vivado / |
| Statement of responsibility, etc |
Majid Pakdel, Electrical, Automation, and Instrumentation Expert at MISCO. |
| 263 ## - PROJECTED PUBLICATION DATE |
|---|
| Projected publication date |
2508 |
| 264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
Hoboken, New Jersey : |
| Name of publisher, distributor, etc |
John Wiley & Sons, Inc., |
| Date of publication, distribution, etc |
[2025] |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 online resource |
| 336 ## - CONTENT TYPE |
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| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
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| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
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| Carrier type term |
online resource |
| Carrier type code |
nc |
| Source |
rdacarrier |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 505 0# - CONTENTS |
|---|
| Miscellaneous information |
Table of Contents<br/>About the Author xi<br/><br/>Preface xii<br/><br/>Acknowledgments xiii<br/><br/>About the Companion Website xiv<br/><br/>1 Overview 1<br/><br/>1.1 Introduction 1<br/><br/>1.2 Introduction to VHDL 2<br/><br/>2 Creating a Project in Vivado 5<br/><br/>2.1 Introduction 5<br/><br/>2.2 Creating a Project 5<br/><br/>3 The VHDL Design Structure 13<br/><br/>3.1 Introduction 13<br/><br/>3.2 The VHDL Keywords 13<br/><br/>3.3 The VHDL Libraries 19<br/><br/>3.4 The VHDL Entities and Architecture 25<br/><br/>3.5 The VHDL Generics 27<br/><br/>4 The VHDL Statements and Data Types 31<br/><br/>4.1 Introduction 31<br/><br/>4.2 The VHDL Data Types 32<br/><br/>4.3 The VHDL Integers 35<br/><br/>4.4 The When-Else Statement 36<br/><br/>4.5 Concurrent Versus Sequential Statements 37<br/><br/>5 The Simulations in Vivado 41<br/><br/>5.1 Introduction 41<br/><br/>5.2 The Shift Register Design 42<br/><br/>5.3 Shift Register Test Bench Design 44<br/><br/>5.4 Vivado Simulator Tool Introduction 46<br/><br/>5.5 Running a Simulation in Vivado 47<br/><br/>5.6 Navigating Vivado Simulations 52<br/><br/>6 The Buttons and LEDs Project 61<br/><br/>6.1 Introduction 61<br/><br/>6.2 Buttons and LEDs Complete Design Walk-through 61<br/><br/>6.3 The Button_LED Arty A7 IO Placement 63<br/><br/>6.4 Generate a Xilinx Programming File 66<br/><br/>6.5 Simulation of Button_LED Project 71<br/><br/>7 The Blinky LEDs Project 75<br/><br/>7.1 Introduction 75<br/><br/>7.2 Constants and Signals 75<br/><br/>7.3 The VHDL Processes 78<br/><br/>7.4 The VHDL If Statements 81<br/><br/>7.5 The If Statement Priority Example 85<br/><br/>7.6 The Blinky LEDs Project IO Placement 90<br/><br/>8 The LED Brightness Project 93<br/><br/>8.1 Introduction 93<br/><br/>8.2 The PWM VHDL Design 94<br/><br/>8.3 The VHDL Generate Statement 101<br/><br/>8.4 The Counter Design 103<br/><br/>8.5 The VHDL Component Instantiations 110<br/><br/>8.6 The LED Brightness Arty A7 IO Placement 120<br/><br/>9 The UART Demonstration Project 125<br/><br/>9.1 Introduction 125<br/><br/>9.2 The MicroBlaze Softcore Processor 129<br/><br/>9.3 The Xilinx Software Development Kit 133<br/><br/>9.4 The UART Demonstration Arty A7 IO Placement 146<br/><br/>10 The UART IO and Register Access 149<br/><br/>10.1 Introduction 149<br/><br/>10.2 The UART IO Complete Design 153<br/><br/>10.3 The UART IO Arty A7 IO Placement 160<br/><br/>11 The ADC Processing Project 163<br/><br/>11.1 Introduction 163<br/><br/>11.2 Using the Xilinx XADC and MicroBlaze MCS 166<br/><br/>11.3 The MicroBlaze MCS ADC Configuration 171<br/><br/>11.4 Interfacing with the XADC Core 172<br/><br/>11.5 The ADC Processing Arty A7 IO Placement 181<br/><br/>12 The SPI Interface Project 183<br/><br/>12.1 Introduction 183<br/><br/>12.2 Overview of the SPI Interface 186<br/><br/>12.3 The SPI Interface Design Strategy 189<br/><br/>12.4 External SPI Flash Chip Memory Organization 191<br/><br/>12.5 The SPI Configuration and File Generation 193<br/><br/>13 Some Miscellaneous Projects with Vivado 197<br/><br/>13.1 Introduction 197<br/><br/>13.2 The I2C Interface Project 197<br/><br/>13.3 The VHDL CORDIC Sine-Cosine Generator 199<br/><br/>13.4 The Trailing Edge PWM in VHDL 204<br/><br/>13.5 The LUT-based Sine Wave in VHDL 219<br/><br/>13.6 The Symmetrical PWM in VHDL 229<br/><br/>14 Generating VHDL Code for Vivado Using Simulink HDL Coder 247<br/><br/>14.1 Introduction 247<br/><br/>14.2 The Half Adder Circuit Design 247<br/><br/>14.3 Sequential Circuit and State Flow Chart Modeling 253<br/><br/>14.4 The Basic PWM Design 262<br/><br/>15 Application of Flowcharts in Simulink for VHDL Code Generation 271<br/><br/>15.1 Flowchart of Multiplier 271<br/><br/>15.2 Flowchart of GCD Calculator 283<br/><br/>15.3 Flowchart of Booth’s Multiplication 291<br/><br/>15.4 Flowchart of an Industrial Control System 299<br/><br/>16 Machine Learning Regression Model on FPGA 311<br/><br/>16.1 Introduction 311<br/><br/>16.2 The Kaggle Dataset 311<br/><br/>16.3 Machine Learning Regression Model for Admission Dataset 311<br/><br/>16.4 The Regression Model in Simulink 316<br/><br/>16.5 Using Generated VHDL Code in Vivado 320<br/><br/>17 Machine Learning Binary Classification Model on FPGA 327<br/><br/>17.1 Introduction 327<br/><br/>17.2 The Kaggle Dataset 327<br/><br/>17.3 The Binary Classification (Logistic Regression) 327<br/><br/>17.4 Machine Learning Logistic Regression Model for Dataset 329<br/><br/>17.5 The Logistic Regression Model in Simulink 337<br/><br/>17.6 Using Generated VHDL Code in Vivado 348<br/><br/>18 Deploying a Deep Neural Network on FPGA 355<br/><br/>18.1 Introduction 355<br/><br/>18.2 The Kaggle Dataset 355<br/><br/>18.3 Introduction to Neural Networks 355<br/><br/>18.4 Piecewise Linear Approximation of Activation Functions 357<br/><br/>18.5 Training the Neural Network Model 368<br/><br/>18.6 Using Generated VHDL Code in Vivado 389<br/><br/>Index 395 |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
"As technology continues to evolve at an unprecedented pace, the ability to effectively design and implement digital systems has become increasingly essential. This book, "Fundamentals of VHDL for FPGA Programming using Vivado," serves as a comprehensive introduction to the fundamental concepts and practical skills necessary for designing digital circuits with VHDL (VHSIC Hardware Description Language) and implementing them on FPGA platforms. My goal is to equip readers with the knowledge required to navigate the complexities of VHDL programming and Vivado design flows, enabling them to bring their innovative ideas to life"-- Provided by publisher. |
| 545 0# - BIOGRAPHICAL OR HISTORICAL DATA |
|---|
| Biographical or historical note |
About the Author<br/>Majid Pakdel received his Master’s degree in Electrical Power Engineering from Isfahan University of Technology, Iran, in 2007, his PhD in Electrical Power Engineering from University of Zanjan in 2018, and his second Masters degree in Computer Engineering-Artificial Intelligence and Robotics from Malek Ashlar University of Technology, Tehran, in 2023. He has published over 20 papers and books in the fields of electrical engineering and computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
VHDL (Computer hardware description language) |
| Authority record control number |
http://id.loc.gov/authorities/subjects/sh89002702 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Field programmable gate arrays |
| Authority record control number |
http://id.loc.gov/authorities/subjects/sh93009062 |
| 655 #4 - INDEX TERM--GENRE/FORM |
|---|
| Genre/form data or focus term |
Electronic books. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
https://onlinelibrary.wiley.com/doi/book/10.1002/9781394343126 |
| Link text |
Full text is available at Wiley Online Library Click here to view |
| 942 ## - ADDED ENTRY ELEMENTS |
|---|
| Source of classification or shelving scheme |
|
| Item type |
EBOOK |