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07695nam a22003497a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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CITU |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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20220420145434.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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220420b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781119377702 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781786300812 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781119377726 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781119377702 |
| 041 ## - LANGUAGE CODE |
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| Language code of text/sound track or separate title |
eng |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition number |
23 |
| 245 ## - TITLE STATEMENT |
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| Title |
Power Systems-On-Chip: |
| Remainder of title |
Practical Aspects of Design / |
| Statement of responsibility, etc |
edited by Bruno Allard. |
| 264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
London, UK : |
| Name of publisher, distributor, etc |
ISTE, |
| Date of publication, distribution, etc |
c2016. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
1 online resource |
| 336 ## - CONTENT TYPE |
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| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
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| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
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| Carrier type term |
online resource |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 490 ## - SERIES STATEMENT |
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| Series statement |
Energy series |
| 500 ## - GENERAL NOTE |
|---|
| General note |
ABOUT THE AUTHOR<br/>Bruno ALLARD, Professor, Electrical Engineering at INSA Lyon and researcher at Ampere-lab, at INSA Lyon, France. |
| 505 0# - CONTENTS |
|---|
| Formatted contents note |
TABLE OF CONTENTS<br/>Preface xi<br/><br/>Introduction xv<br/>Bruno ALLARD<br/><br/>Chapter 1. Control Strategies and CAD Approach 1<br/>Pedro ALOU, José A. COBOS, Jesus A. OLIVER, Bruno ALLARD, Benôit LABBE, Aleksandar PRODIC and Aleksandar RADIC<br/><br/>1.1. Objectives 2<br/><br/>1.2. Operation principle of three non-isolated converters 8<br/><br/>1.2.1. Buck converter operation 8<br/><br/>1.2.2. Boost converter operation 10<br/><br/>1.2.3. Buck-boost converter operation 11<br/><br/>1.3. Power stage 13<br/><br/>1.3.1. MOSFET switching an inductive load 13<br/><br/>1.3.2. Extracting the parasitic capacitance values using simulations 18<br/><br/>1.3.3. Power-stage design issues 19<br/><br/>1.3.4. Segmented power stage and multiphase operation 21<br/><br/>1.3.5. LC filter design space 22<br/><br/>1.4. Control stage 29<br/><br/>1.4.1. Voltage-mode control of the buck converter 29<br/><br/>1.4.2. The RHP zero of the boost converter 35<br/><br/>1.4.3. Current-mode control 37<br/><br/>1.4.4. Hysteretic and sliding-mode control 40<br/><br/>1.4.5. Ripple-based controls for fast dynamics 45<br/><br/>1.4.6. V1 concept: description and applicability 52<br/><br/>1.4.7. Overview of the synchronization of asynchronous modulations 59<br/><br/>1.4.8. PFM - pulse skipping: burst modes 62<br/><br/>1.5. Minimum voltage deviation controller 63<br/><br/>1.5.1. Introduction 64<br/><br/>1.5.2. Integrated circuit implementation and experimental results 67<br/><br/>1.6. CAD tools for PwrSoC design and optimization 69<br/><br/>1.6.1. Overview of the CAD requirements 71<br/><br/>1.6.2. Loss models for integrated inductors and semiconductors 73<br/><br/>1.6.3. Optimization algorithms 82<br/><br/>1.6.4. Outcome of the optimization (topology, area, loss, fsw, detailed design) 84<br/><br/>1.6.5. Impact of technology 87<br/><br/>1.7. Conclusion 91<br/><br/>Chapter 2. Magnetic Components for Increased Power Density 93<br/>Santosh KULKARNI and Cian O’MATHUNA<br/><br/>2.1. Commercial and research trends towards PwrSiP and PwrSoC 96<br/><br/>2.2. Review of magnetics 104<br/><br/>2.2.1. Micro-inductor structures 104<br/><br/>2.2.2. Magnetic materials and processing for thin film integrated micro-magnetic devices 111<br/><br/>2.3. Figures of merit for performance of integrated magnetics 118<br/><br/>2.3.1. Figure of merit – DC performance 118<br/><br/>2.3.2. Figure of merit and AC performance 123<br/><br/>2.4. Technology roadmap and challenges 123<br/><br/>2.4.1. Market drivers 124<br/><br/>2.4.2. PwrSoC supply chain challenges 126<br/><br/>2.4.3. PwrSoC technology platform 127<br/><br/>2.4.4. Integrated magnetic devices for PwrSoC – opportunities 128<br/><br/>2.5. Conclusions 130<br/><br/>2.6. Acknowledgments 132<br/><br/>Chapter 3. Dielectric Components for Increased Power Density 133<br/>Frédéric VOIRON<br/><br/>3.1. Introduction 133<br/><br/>3.2. Basics of dielectric physics 135<br/><br/>3.2.1. Forewords 135<br/><br/>3.2.2. Polarization, dipole and capacitance 135<br/><br/>3.2.3. Polarization mechanisms in dielectrics 136<br/><br/>3.2.4. Losses in dielectrics 139<br/><br/>3.3. Silicon integrated capacitors 140<br/><br/>3.3.1. Integrated capacitors for enhanced performance 141<br/><br/>3.4. Integrated capacitors for enhanced reliability 145<br/><br/>3.4.1. Dielectric processing 145<br/><br/>3.4.2. Lifetime considerations 149<br/><br/>3.5. Integrated capacitor optimization for power switching 150<br/><br/>3.5.1. Regular layout 150<br/><br/>3.5.2. Broad band modeling 150<br/><br/>3.5.3. Capacitance parasitic suppression 153<br/><br/>3.6. Conclusion 154<br/><br/>Chapter 4. On-board Power Management DC/DC Inductive Converter 157<br/>Benoît LABBE and Bruno ALLARD<br/><br/>4.1. Specifications 157<br/><br/>4.1.1. Load-related requirements 158<br/><br/>4.1.2. System-related requirements 159<br/><br/>4.1.3. Power delivery network 161<br/><br/>4.2. Current-mode sliding-mode control implementation 161<br/><br/>4.2.1. System analysis: voltage regulation loops 162<br/><br/>4.2.2. System analysis: loop delay control 167<br/><br/>4.2.3. System analysis: switching frequency control 168<br/><br/>4.2.4. Design 169<br/><br/>4.2.5. Results 172<br/><br/>4.3. Conclusions . 174<br/><br/>Chapter 5. On-Chip Power Management DC/DC Switched-Capacitor Converter 179<br/>Gael PILLONNET, Thomas SOUVIGNET and Bruno ALLARD<br/><br/>5.1. Topology description 180<br/><br/>5.1.1. Ratio calculation 180<br/><br/>5.1.2. Basic scheme 182<br/><br/>5.1.3. Steady-state modeling 183<br/><br/>5.2. Pros and cons 190<br/><br/>5.2.1. Key advantages 190<br/><br/>5.2.2. Main disadvantages 192<br/><br/>5.3. State-of-the-art 193<br/><br/>5.3.1. Research scope and main focus 194<br/><br/>5.3.2. Integration level 194<br/><br/>5.3.3. The point-of-load (POL) application 195<br/><br/>5.4. Design example 204<br/><br/>5.4.1. Landscape of demonstrated solutions 204<br/><br/>5.4.2. Selected architecture 207<br/><br/>Chapter 6. High-Switching Frequency Inductive DC/DC Converters 213<br/>Christian MARTIN, Florian NEVEU and Bruno ALLARD<br/><br/>6.1. Context and topologies 214<br/><br/>6.1.1. Discussion on figures of merit 219<br/><br/>6.1.2. Outstanding state-of-the-art performances 224<br/><br/>6.2. Cascode power stage 225<br/><br/>6.3. High-quality decoupling 229<br/><br/>6.4. Design considerations for passive components 232<br/><br/>6.5. Integrated inductor characterization 235<br/><br/>6.5.1. Harmonic characterization 235<br/><br/>6.5.2. Time-domain characterization 237<br/><br/>6.5.3. Converter experimental characterization 242<br/><br/>6.6. Conclusion 246<br/><br/>6.7. Acknowledgments 247<br/><br/>Chapter 7. Hybrid and Multi-level Converter Topologies for On-Chip Implementation of Reduced Voltage-Swing Converters 249<br/>Aleksandar PRODIC, Sheikh Mohammad AHSANUZZAMAN, Behzad MAHDAVIKHAH and Timothy MCRAE<br/><br/>7.1. Introduction 249<br/><br/>7.1.1. Inductor volume reduction through voltage swing minimization 251<br/><br/>7.2. Cascaded hybrid SC-inductive topologies 254<br/><br/>7.2.1. Merged switched-capacitor multi-phase buck (MSCB) converter 255<br/><br/>7.3. Hybrid serial input/output converters 262<br/><br/>7.3.1. HSI/O power processing efficiency and power division 265<br/><br/>7.3.2. Switched-capacitor conversion ratio 267<br/><br/>7.3.3. Passive volume and switch voltage stress 269<br/><br/>7.4. An on-chip integrated high-density power management solution for portable applications based on a multi-output switched-capacitor circuit 270<br/><br/>7.5. Multi-level and flying capacitor multi-level converters 279<br/><br/>7.6. Conclusion 282<br/><br/>Bibliography 285<br/><br/>List of Acronyms 311<br/><br/>List of Authors 315<br/><br/>Index 317 |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
DESCRIPTION<br/>The book gathers the major issues involved in the practical design of Power Management solutions in wireless products as Internet-of-things. Presentation is not about state-of-the-art but about appropriation of validated recent technologies by practicing engineers. The book delivers insights on major trade-offs and a presentation of examples as a cookbook. The content is segmented in chapters to make access easier for the lay-person. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Electronic circuit design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Systems on a chip |
| General subdivision |
Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Printed circuits |
| General subdivision |
Design and construction. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Allard, Bruno, |
| Dates associated with a name |
1965- |
| Relator term |
editor |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
https://onlinelibrary.wiley.com/doi/book/10.1002/9781119377702 |
| Link text |
Full text available at Wiley Online Library Click here to view |
| 942 ## - ADDED ENTRY ELEMENTS |
|---|
| Source of classification or shelving scheme |
|
| Item type |
EBOOK |